Name
Title | ||
|---|---|---|
Application of Generalised Reed-Muller Expansion in Development of Programmable Logic Array |
Abstract | ||
|---|---|---|
The intensive development of information technologies and the need to process big information and data lead to elaboration of new technologies in the hardware design. One of the important aspects here is to increase the information capacity of gates and interconnections that is possible by application of non-binary elements. Employing non-binary (Many-Valued) cells as computing and memory units enables to pack unprecedented high-density information. In turn, use of non-binary units calls for development of new methods in logic design. These methods should be based on a non-binary logic and application of Multiple-Valued Logic in design of non-binary logical circuits and networks. In this paper, a new technique of the Programmable Logic Array design based on Many-Valued units is considered. This technique is based on the use of generalised Reed-Muller expansion of Multi-Valued Logic function representation. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/IDAACS.2019.8924457 | 2019 10th IEEE International Conference on Intelligent Data Acquisition and Advanced Computing Systems: Technology and Applications (IDAACS) |
Keywords | Field | DocType |
generalised Reed-Muller expansion,logic circuit,multiple-valued logic,programmable logic arrays | Logic synthesis,Logic gate,Computer architecture,Information technology,Computer science,Programmable logic array,Emerging technologies,Artificial intelligence,Electronic circuit,Function representation,Machine learning | Conference |
Volume | ISBN | Citations |
2 | 978-1-7281-4070-4 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Elena N. Zaitseva | 1 | 53 | 14.38 |
| Vitaly G. Levashenko | 2 | 39 | 12.90 |
| Igor Lukyanchuk | 3 | 0 | 0.34 |
| Miroslav Kvassay | 4 | 9 | 8.85 |
| Jan Rabcan | 5 | 0 | 1.01 |
| Patrik Rusnak | 6 | 0 | 0.68 |