Paper Info
Title
FPGA Design and Implementation of an AES Algorithm based on Iterative Looping Architecture
Abstract
Most applications nowadays require protection of their data from tampering to ensure secure transfer of information. At the same time, they need to be secured quickly and within available resources. In this paper, efficient hardware architecture has been designed and implemented for the Advanced Encryption Standard (AES) algorithm based on the Field Programmable Gate Array (FPGA) using High Level Language (HLL). The design focused on the optimal use of available resources, thus iterative looping architecture is suggested to minimize the hardware resources utilization and power consumption. The design is synthesized and simulated using Xilinx ISE 14.7 and ModelSim software, respectively. The implementation is compared with other previous works in terms of area, and power consumption. The results show that the proposed design achieves significant decrease in area (utilize 423 slices) and power consumption (3.68 W). The throughput reaches the value of 2457 Mbit/Sec implemented on Virtex-6 xc6vlx195t-3 of Xilinx device family. This makes the proposed design suitable for applications, where resources are limited.
Year
DOI
Venue
2019
10.1109/ICCE-Berlin47944.2019.8966137
2019 IEEE 9th International Conference on Consumer Electronics (ICCE-Berlin)
Keywords
Field
DocType
Advanced Encryption Standard (AES),High Level Language (HLL),Integrated Synthesis Environment (ISE),Field Programmable Gate Array (FPGA)
ModelSim,Advanced Encryption Standard,Computer science,Algorithm,Field-programmable gate array,High-level programming language,Software,Throughput,Megabit,Hardware architecture
Conference
ISSN
ISBN
Citations 
2166-6814
978-1-7281-2775-0
0
PageRank 
References 
Authors
0.34
2
3
Name
Order
Citations
PageRank
Alshaima Q. Al-Khafaji100.34
Mohammed Falih Al-Gailani200.34
Hikmat N. Abdullah300.68