Paper Info
Title
A Pre-Emphasis Pulse Generator Insensitive to Process Variation for Driving Large Memory and Panel Display Arrays with Minimal Delay Time
Abstract
A pre-emphasis pulse generator is proposed which can provide minimal word-line or column-line delay time in a large memory array or panel display without calibration even under a large process variation. The optimum pre-emphasis pulse width is theoretically identified by monitoring the far-end of the delay line to reach a certain value which does not include the parasitic resistance and capacitance of the delay line but only includes an amount of overdrive. The circuit was fabricated together with the delay line in 0.18 μm 3V CMOS. Even with RC variation of 20%, the proposed circuit reduced the delay time by 60% with 60% overdrive in comparison with a fixed pre-emphasis pulse width without any calibration prior user operation or any special test sequence in die test. Sensitivity of a variation in a reference voltage and a comparator offset on the delay time is also discussed. Furthermore, the optimum detection level is presented in case that the resistance of driver and switch is as high as that of the delay line.
Year
DOI
Venue
2019
10.1109/APCCAS47518.2019.8953167
2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Keywords
Field
DocType
RC lines,Delay time,Pre-emphasis,Large memory,Panel display,Word-line,Column-line
Parasitic element,Comparator,Control theory,Computer science,Voltage reference,Pulse-width modulation,Electronic engineering,CMOS,Pulse generator,Process variation,Emphasis (telecommunications)
Conference
ISBN
Citations 
PageRank 
978-1-7281-2941-9
0
0.34
References 
Authors
1
2
Name
Order
Citations
PageRank
Kazuki Matsuyama100.34
Toru Tanzawa26614.08