Title
A Novel Hardware Architecture for Human Detection using HOG-SVM Co-Optimization
Abstract
Histogram of Oriented Gradient (HOG) in combination with Supported Vector Machine (SVM) has been used as an efficient method for object detection in general and human detection in particular. Human detection using HOG-SVM in hardware shows high classification rate at higher throughput when compared with deep learning methods. However, data dependencies and complicated arithmetic in HOG feature generation and SVM classification limit the maximum throughput of these applications. In this paper, we propose a novel high-throughput hardware architecture for human detection by co-optimizing HOG feature generation and SVM classification. The throughput is improved by using a fast, highly-parallel and low-cost HOG feature generation in combination with a modified datapath for parallel computation of SVM and HOG feature normalization. The proposed architecture has been implemented in TSMC 65nm technology with a maximum operating frequency of 500MHz and throughput of 139fps for Full-HD resolution. The hardware area cost is about 145kGEs along with 242kb SRAMs.
Year
DOI
Venue
2019
10.1109/APCCAS47518.2019.8953123
2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Keywords
Field
DocType
Artificial Intelligence,Histogram of Oriented Gradient,Support Vector Machine,HOG,SVM
Object detection,Histogram,Datapath,Normalization (statistics),Pattern recognition,Computer science,Support vector machine,Electronic engineering,Artificial intelligence,Deep learning,Throughput,Hardware architecture
Conference
ISBN
Citations 
PageRank 
978-1-7281-2941-9
0
0.34
References 
Authors
6
3
Name
Order
Citations
PageRank
Ngo-Doanh Nguyen100.68
Duy-Hieu Bui2132.83
Xuan-Tu Tran39111.87