Name
Abstract | ||
|---|---|---|
As the switching frequency of DC-DC converters continues to increase, the influence of circuit delays is also increasing, which poses a great challenge to the design of a comparator. A 30MHz delay-line-based buck converter is proposed in this paper, which eliminates the need for a traditional PWM comparator, simplifies the complexity of the circuit and logic and solves a series of problems caused by comparator delays at high switching frequency. A delay-line-based voltage-to-duty-cycle (V2D) controller is used to replace the traditional ramp-comparator-based V2D controller to achieve a wider duty cycle range. The proposed DC-DC converter has been designed and simulated by Cadence software based on the 0.18-μm mixed signal CMOS process. The tunable duty cycle ranges from 5.7% to 94.8%, allowing the converter to regulate the output from 0.1V to 1.7V with 1.8V input. With a step of 400mA in the load current, the setting time is around 2μs. The maximum load current is 1A and the peak efficiency is as high as 94.5% with 1.5V output. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/APCCAS47518.2019.8953135 | 2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS) |
Keywords | Field | DocType |
DC-DC converters,circuit delays,delay-line-based,high switching frequency,voltage-to-duty-cycle (V2D) | Control theory,Comparator,Duty cycle,Computer science,Pulse-width modulation,Electronic engineering,Converters,Mixed-signal integrated circuit,Buck converter,AND gate | Conference |
ISBN | Citations | PageRank |
978-1-7281-2941-9 | 0 | 0.34 |
References | Authors | |
7 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhang Zhang | 1 | 5 | 8.09 |
| Shu Xu | 2 | 0 | 0.34 |
| Fangzhou Yao | 3 | 0 | 0.34 |
| Guangjun Xie | 4 | 29 | 9.64 |
| Xin Cheng | 5 | 1 | 7.17 |