Title
Analog Implementation of Reconfigurable Convolutional Neural Network Kernels
Abstract
This paper presents a neuromorphic circuit implementation of a 3x3 CNN convolution kernel that consists of 9 four-quadrant analog multipliers and one ReLU analog circuit unit. The kernel circuit is powered by a single power supply of 1.2V and the inputs can be both negative and positive values centered at VDD/2 or 600mV with a dynamic range of ± 100mV. The multiplier can achieve an equivalent precision of 4-bit of a digital multiplier, and the ReLU can achieve the perfect rectification of input values. The complete kernel circuit is designed with SMIC (Semiconductor Manufacturing International Corporation) 55nm CMOS LP process and the power consumption of the multiplier and ReLU is less than 13.2μW and 14.4μW respectively under full input swing. The analog kernel is also reconfigurable to construct any size of convolution kernel matrix.
Year
DOI
Venue
2019
10.1109/APCCAS47518.2019.8953177
2019 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS)
Keywords
Field
DocType
convolution kernel,CNN,multiplier,activation function,ReLU,analog CMOS
Kernel (linear algebra),Dynamic range,Convolutional neural network,Computer science,Semiconductor device fabrication,Neuromorphic engineering,Electronic engineering,Multiplier (economics),CMOS,Kernel (image processing)
Conference
ISBN
Citations 
PageRank 
978-1-7281-2941-9
0
0.34
References 
Authors
3
5
Name
Order
Citations
PageRank
Jianghan Zhu121.74
Yucong Huang200.34
Zhitao Yang311.73
Xiaoying Tang488.79
Terry Tao Ye500.34