Name
Abstract | ||
|---|---|---|
In fine line technology, pipeline ADC performance improvement is difficult and power consumption becomes more considerable. In this context, digital calibration algorithm is applied to improve system performance and reduce power consumption. In order to verify pipeline ADC digital calibration technology before chip verification, to evaluate power consumption and hardware overhead, an FPGA based verification platform is established. In this platform, ADC digital model is established to simulate the actual ADC, digital calibration algorithm is described by digital calibration module, and the ideal ADC is used to provide input signal for the system. Applying this platform, simulation is carried out in a deterministic digital calibration technique. The simulation results show that, by applying of the platform, the correctness and reliability of the design of pipeline ADC digital calibration system can be effectively improved, and the system developing cycle can be shortened. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ASICON47005.2019.8983587 | 2019 IEEE 13TH INTERNATIONAL CONFERENCE ON ASIC (ASICON) |
Field | DocType | ISSN |
Calibration algorithm,Computer science,Fine line,Correctness,Field-programmable gate array,Real-time computing,Chip,Computer hardware,Calibration,Performance improvement,Power consumption | Conference | 2162-7541 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Yuehong Gang | 1 | 0 | 0.34 |
| Min Luo | 2 | 0 | 0.34 |
| Mingyu Wang | 3 | 135 | 24.90 |