Name
Title | ||
|---|---|---|
Balance of memory footprint and runtime for high-density routing in large-scale FPGAs |
Abstract | ||
|---|---|---|
The scale of modern FPGAs is expanding and applications on FPGA are becoming more and more complex. Applications requiring high-density routing in large-scale FPGA determine that CAD tools not only require large memory consumption, but also require long routing runtime. This paper proposes a method to describe the regularity of interconnect resources in CB/SB structure, and then applies a two-level template method to store the routing resource graph (RRG) which describes the detailed FPGA interconnect resources. This algorithm fully considers the high regularity of interconnect resources in large-scale FPGAs with CB/SB structure, memory footprint could be reduced. At the same time, RRG created by this method does not affect the routing search space, thus routing runtime will not change significantly. Implementation of the algorithm on VPR platform shows a memory reduction of 1.83X could be achieved at a routing runtime penalty of 1.07X. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ASICON47005.2019.8983426 | 2019 IEEE 13th International Conference on ASIC (ASICON) |
Keywords | Field | DocType |
CB-SB structure,FPGA interconnect resources,routing runtime penalty,memory reduction,routing search space,RRG,routing resource graph,two-level template method,long routing runtime,memory consumption,CAD tools,large-scale FPGA,high-density routing,memory footprint | Fpga interconnect,Cad tools,Graph,Computer science,High density,Field-programmable gate array,Real-time computing,Memory footprint,Interconnection,Embedded system | Conference |
ISSN | ISBN | Citations |
2162-7541 | 978-1-7281-0736-3 | 0 |
PageRank | References | Authors |
0.34 | 0 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Wei Liu | 1 | 38 | 8.58 |
| Weilin Cong | 2 | 0 | 0.34 |
| Chengyu Hu | 3 | 132 | 28.60 |
| Peng Lu | 4 | 126 | 17.62 |
| Jinmei Lai | 5 | 145 | 20.38 |