Name
Abstract | ||
|---|---|---|
Security concerns for field-programmable gate array (FPGA) applications and hardware are evolving as FPGA designs grow in complexity, involve sophisticated intellectual properties (IPs), and pass through more entities in the design and implementation flow. FPGAs are now routinely found integrated into system-on-chip (SoC) platforms, cloud-based shared computing resources, and in commercial and government systems. The IPs included in FPGAs are sourced from multiple origins and passed through numerous entities (such as design house, system integrator, and users) through the lifecycle. This paper thoroughly examines the interaction of these entities from the perspective of the bitstream file responsible for the actual hardware configuration of the FPGA. Five stages of the bitstream lifecycle are introduced to analyze this interaction: 1) bitstream-generation, 2) bitstream-at-rest, 3) bitstream-loading, 4) bitstream-running, and 5) bitstream-end-of-life. Potential threats and vulnerabilities are discussed at each stage, and both vendor-offered and academic countermeasures are highlighted for a robust and comprehensive security assurance. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ITC44170.2019.9000145 | 2019 IEEE International Test Conference (ITC) |
Keywords | Field | DocType |
FPGA Security,Encryption,Bitstream Protection | Computer science,Software security assurance,Integrator,Field-programmable gate array,Real-time computing,Encryption,Gate array,Bitstream,Cloud computing,Embedded system,Vulnerability | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-7281-4824-3 | 1 |
PageRank | References | Authors |
0.35 | 24 | 5 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Adam Duncan | 1 | 1 | 1.37 |
| Fahim Rahman | 2 | 1 | 1.03 |
| Andrew Lukefahr | 3 | 153 | 7.08 |
| Farimah Farahmandi | 4 | 78 | 11.82 |
| Mohammad Tehranipoor | 5 | 3181 | 243.40 |