Name
Abstract | ||
|---|---|---|
Hardware security adds another dimension to the design space, and more and more attention is paid to protect a circuit against various types of attacks like sniffing, spoofing or IP theft. However, all the efforts for security taken by a designer might be sacrificed by afterwards integrating infrastructure for test, diagnosis and reliability management. Especially, access mechanisms like reconfigurable scan networks (RSNs) may open options for side-channel attacks. Using the presented approach an accurate estimation of reachability properties of all considered benchmarks is provided. The method uses a matrix-based reachability analysis of the original design and the augmented design. The reachability analysis covers complex functional dependencies, caused by configuring a single scan path as well as multiple sequentially activated scan paths through the RSN. This approach adds acceptable runtime to the security verification flow of the design, and shows the designer the introduced possible security violations. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/ITC44170.2019.9000114 | 2019 IEEE International Test Conference (ITC) |
Keywords | Field | DocType |
Reconfigurable Scan Networks,Side-Channel Attacks,Security Validation | Design space,Hardware security module,Spoofing attack,Computer science,Real-time computing,Functional dependency,Reachability,Side channel attack,Reliability management,Embedded system,Security compliance | Conference |
ISSN | ISBN | Citations |
1089-3539 | 978-1-7281-4824-3 | 0 |
PageRank | References | Authors |
0.34 | 10 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Natalia Lylina | 1 | 0 | 2.37 |
| Ahmed Atteya | 2 | 0 | 2.03 |
| Pascal Raiola | 3 | 3 | 2.77 |
| Matthias Sauer | 4 | 195 | 20.02 |
| Bernd Becker | 5 | 855 | 73.74 |
| Hans-Joachim Wunderlich | 6 | 1 | 2.38 |