Paper Info
Title
waveSZ - a hardware-algorithm co-design of efficient lossy compression for scientific data.
Abstract
Error-bounded lossy compression is critical to the success of extreme-scale scientific research because of ever-increasing volumes of data produced by today's high-performance computing (HPC) applications. Not only can error-controlled lossy compressors significantly reduce the I/O and storage burden but they can retain high data fidelity for post analysis. Existing state-of-the-art lossy compressors, however, generally suffer from relatively low compression and decompression throughput (up to hundreds of megabytes per second on a single CPU core), which considerably restrict the adoption of lossy compression by many HPC applications especially those with a fairly high data production rate. In this paper, we propose a highly efficient lossy compression approach based on field programmable gate arrays (FPGAs) under the state-of-the-art lossy compression model SZ. Our contributions are fourfold. (1) We adopt a wavefront memory layout to alleviate the data dependency during the prediction for higher-dimensional predictors, such as the Lorenzo predictor. (2) We propose a co-design framework named waveSZ based on the wavefront memory layout and the characteristics of SZ algorithm and carefully implement it by using high-level synthesis. (3) We propose a hardware-algorithm co-optimization method to improve the performance. (4) We evaluate our proposed waveSZ on three real-world HPC simulation datasets from the Scientific Data Reduction Benchmarks and compare it with other state-of-the-art methods on both CPUs and FPGAs. Experiments show that our waveSZ can improve SZ's compression throughput by 6.9X ~ 8.7X over the production version running on a state-of-the-art CPU and improve the compression ratio and throughput by 2.1X and 5.8X on average, respectively, compared with the state-of-the-art FPGA design.
Year
DOI
Venue
2020
10.1145/3332466.3374525
PPoPP '20: 25th ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming San Diego California February, 2020
Keywords
Field
DocType
Lossy Compression, FPGA, Software-Hardware Co-Design, Scientific Data, Compression Ratio, Throughput
Data dependency,Lossy compression,Megabyte,Computer science,Parallel computing,Field-programmable gate array,Compression ratio,Throughput,Multi-core processor,Data reduction
Conference
ISBN
Citations 
PageRank 
978-1-4503-6818-6
1
0.35
References 
Authors
0
8
Name
Order
Citations
PageRank
Jiannan Tian110.35
Sheng Di273755.88
Chengming Zhang353.10
Xin Liang410712.74
Sian Jin583.16
Dazhao Cheng610711.72
Dingwen Tao712917.66
Franck Cappello83775251.47