Paper Info
Title
DC Fault Analysis Models of Three Converter Topologies Considering Control Effects
Abstract
Existing converter models are normally reduced as simplified electrical components, whereas it overlooks the impacts of fast dynamics of converter current control loops. Therefore, the dc fault current calculation with the traditional simplified converter models becomes invalid when the simulation time is longer. To overcome this problem, this article incorporates the control effects of converters during the transient process and proposes three dc fault analysis models of classical three converter topologies for the high-voltage dc (HVdc) application including line communicated converter (LCC), two-level voltage-source converter (VSC), and modular multilevel converter (MMC). For an LCC-based rectifier, the nonlinear part of original model is first linearized with the least square method due to the large dc-link voltage deviation during dc fault, and the proportional integral (PI) current regulator with the reduced linearized model can be equivalent as an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RC</italic> circuit for dc fault analysis. However, for two-level VSC or MMC, the dc-link voltage deviation does not drop that much with a large dc-link capacitor discharging process during transient dynamics. As a result, the original model is linearized relying on the small-signal method based on prefault operation points, and the dynamics of fast inner current loop with the linearized model can be represented as an <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RL</italic> circuit for dc fault current calculation. for dc fault analysis The proposed dc fault analysis models of three converters as equivalent <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RLC</italic> circuits are well testified under different fault resistances and dc reactors, control parameters, and operating conditions. Moreover, dc fault simulations of a hybrid HVdc system have verified the effectiveness of the proposed converter models.
Year
DOI
Venue
2020
10.1109/TIE.2019.2956376
IEEE Transactions on Industrial Electronics
Keywords
DocType
Volume
Circuit faults,Fault currents,Rectifiers,Analytical models,Integrated circuit modeling,HVDC transmission,Mathematical model
Journal
67
Issue
ISSN
Citations 
11
0278-0046
0
PageRank 
References 
Authors
0.34
0
6
Name
Order
Citations
PageRank
Yujun Li110418.20
Jiapeng Li2184.13
Guihong Wu300.34
Liansong Xiong431.48
Ke Jia500.34
Zhou Xu66615.44