Name
Abstract | ||
|---|---|---|
A major issue faced by data scientists today is how to scale up their processing infrastructure to meet the challenge of big data and high-performance computing (HPC) workloads. With today's HPC domain, it is required to connect multiple graphics processing units (GPUs) to accomplish large-scale parallel computing along with CPUs. Data movement between the processor and on-chip or off-chip memory ... |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1049/iet-cdt.2019.0092 | IET Computers & Digital Techniques |
Keywords | Field | DocType |
cache storage,computer architecture,DRAM chips,graphics processing units,multiprocessing systems,parallel processing | Memory protection,Dynamic random-access memory,Computer architecture,Central processing unit,Computer science,Cache,Parallel computing,Symmetric multiprocessor system,Memory management,Hardware acceleration,Memory management unit | Journal |
Volume | Issue | ISSN |
14 | 2 | 1751-8601 |
Citations | PageRank | References |
1 | 0.36 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Anakhi Hazarika | 1 | 1 | 0.36 |
| Soumyajit Poddar | 2 | 3 | 2.78 |
| Hafizur Rahaman | 3 | 368 | 91.37 |