Paper Info
Title
An efficient NoC router design by using an enhanced AES with retiming and clock gating techniques
Abstract
AbstractAbstractA system‐on‐a‐chip (SoC) processor core contains several numbers of chips integrated into a single chip where each and every integrated circuit (IC) consists of multiple blocks. Hence, data routing from one chip to another creates a difficult issue in the SoC. A network‐on‐a‐chip (NoC) router has been mainly used to obtain highly reliable data transmission from a source to a destination using low power, low hardware complexity, and high speed to achieve efficient routing in the SoC core, which contains a router, network links (NLs), and network interface (NI). The heart of the NoC core, ie, the router, consists of a finite state machine (FSM), input/output FIFO, a crossbar switch, and an arbiter; however, the XY routing technique was incorporated into the NoC router to achieve high switching speed, and the FSM is used as a controller for the router along with the data stored in FIFO. The multiplexing and demultiplexing operations were also carried out in the crossbar switch in which a grant signal is being generated using the compact round‐robin arbiter and an Advanced Encryption Standard (AES) scheme, which is incorporated into the NoC router to achieve high reliability. The chief goal is to establish an efficient NoC router using an improved AES algorithm to achieve high reliability, small chip size, low power consumption, and high performance. Similarly, an optimized composite S‐box is designed using a compact multiplicative inverse unit with an improved inverse MixColumns structure proposed using compact 09, 0b, 0d, and 0e operations and retiming pipelined inclusively with clock gating methods (CGMs) applied in the targeted AES scheme. Hence, the retiming method can be used to shrink the number of registers by placing the register in an optimum location with low area and power in retiming‐based AES. The switching activity of the clock signal is reduced by using the CGM, which has low power consumption and high speed for clock gating–based AES. Therefore, the high performance–based AES is designed using a pipelined technique with high chip size and power due to the insertion of a large number of registers into the AES circuits. Five types of AES structures are designed, and the die size, delay, power, and 90% security with an optimized AES technique incorporated into a 3×3 NoC router with mesh topology are analyzed. Finally, the comparison between the existing and proposed NoC routers was carried out to analyze the area, delay, and power (ADP) product, and the NoC router design was formulated using Verilog HDL, and limitations along the synthesis process were executed using a ModelSim and Xilinx ISE tools. View Figure In this proposed algorithm of the NoC router, an optimized AES has been incorporated into the NoC router instead of regular AES structure. The C‐S‐box structures consist of isomorphic mapping, inverse isomorphic mapping, inverse affine transformation, affine transformation, and MI. A C‐S‐box was designed using an optimized MI unit and four transistors XOR gates instead of six transistors XOR gates. The proposed C‐S‐box provides low chip size and low power consumption along with higher speed than the existing linearity S‐box and existing C‐S‐box.
Year
DOI
Venue
2020
10.1002/ett.3839
Periodicals
DocType
Volume
Issue
Journal
31
12
ISSN
Citations 
PageRank 
2161-3915
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
N.L. Venkataraman100.34
Ravi Kumar2214.89