Title
An Efficient Adaptive Importance Sampling Method for SRAM and Analog Yield Analysis
Abstract
Performance failure has become a major threat for various memory and analog circuits. It is challenging to estimate the extremely small failure probability when failed samples are distributed in multiple disjoint regions. In this article, we propose an adaptive importance sampling (AIS) algorithm. AIS has several iterations of sampling region adjustments, while existing methods predecide a static sampling distribution. We design two adaptive frameworks based on resampling and population Metropolis-Hastings (MH) to iteratively search for failure regions. The experimental results of the AIS method exhibit better efficiency and higher accuracy. For SRAM bit cell with single failure region, the AIS method uses 2-$27{\times }$ fewer samples and reaches better accuracy when compared to several recent methods. For a two-stage amplifier circuit with multiple failure regions, the AIS method is $90{\times }$ faster than Monte Carlo and 7-23 ${\times }$ over other methods. For charge pump circuit and $C^{2}MOS$ master-slave latch circuit, the AIS method can reach 6-$18{\times }$ and 4-$6{\times }$ speedup over other methods, respectively.
Year
DOI
Venue
2020
10.1109/TCAD.2020.2966481
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Keywords
DocType
Volume
Adaptive importance sampling (AIS),failure probability,failure regions,Metropolis–Hastings (MH),process variation,resampling
Journal
39
Issue
ISSN
Citations 
12
0278-0070
1
PageRank 
References 
Authors
0.35
0
6
Name
Order
Citations
PageRank
Shi Xiao195.97
Hao Yan212.38
Jinxin Wang310.35
Jiajia Zhang42616.64
Longxing Shi511639.08
Lei He6167.77