Name
Abstract | ||
|---|---|---|
The binary information technology reaches its limits set by the atomic size miniaturization, by calculation speed and by the fundamental principle of energy dissipation per bit processing. Employing multiple-valued logic (MVL) cells as computing and memory units reduces energy losses and enables to pack of unprecedented high-density information, but the current silicon-based material technologies have been studied marginally for the material realization of MVL devices. Here, we propose to use the ferroelectrics for the implementation of MVL units using their ability to pin the polarization as a sequence of multistable states. More specifically, the realization of a programmable logic array (PLA) based on MVL units is considered with the application of the ferroelectrics technology in implementation of memory units. The specific of the PLA construction is the use of generalized Reed-Muller expression for the representation of an MVL function. In this article, several possible implementations of such PLAs are considered, and their properties are analyzed from the logic design point of view. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCAD.2020.2966676 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Generalized Reed-Muller expression (GRME),logic circuit,multiple-valued logic (MVL),programmable logic array (PLA) | Journal | 39 |
Issue | ISSN | Citations |
12 | 0278-0070 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Vitaly G. Levashenko | 1 | 39 | 12.90 |
| Igor Lukyanchuk | 2 | 0 | 0.34 |
| Elena N. Zaitseva | 3 | 53 | 14.38 |
| Miroslav Kvassay | 4 | 9 | 8.85 |
| Jan Rabcan | 5 | 0 | 2.37 |
| Patrik Rusnak | 6 | 1 | 3.48 |