Name
Abstract | ||
|---|---|---|
The tunnel field-effect transistor (TFET) is one of the promising transistors which is expected to replace some complementary metal-oxide semiconductor (CMOS) circuits. Here, we apply a SPICE simulation of a Si TFET using high-K gate insulator to a simple circuit of 32-kHz crystal oscillator and compare the power consumption of Si TFET with conventional CMOSs calculated from the predictive transistor model (PTM). We considered L = 65-nm and L = 90-nm devices based on a table model whose values are derived from technology computer aided design (TCAD) calculations. We show that the power consumptions of TFETs are about 22.3%similar to 38.6% lower than those of CMOSs for L = 65-nm devices, and we show the 13.6%similar to 36.1% lower power consumption of TFETs for L = 90-nm devices. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1587/elex.17.20200025 | IEICE ELECTRONICS EXPRESS |
Keywords | DocType | Volume |
tunnel field-effect transistor (TFET), crystal oscillation, CMOS, IoT | Journal | 17 |
Issue | ISSN | Citations |
6 | 1349-2543 | 0 |
PageRank | References | Authors |
0.34 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Tetsufumi Tanamoto | 1 | 24 | 6.40 |
| Chika Tanaka | 2 | 0 | 0.34 |
| Shinichi Takagi | 3 | 3 | 9.69 |