Name
Title | ||
|---|---|---|
Design and Evaluation of Low-Complexity Radiation Hardened CMOS Latch for Double-Node Upset Tolerance |
Abstract | ||
|---|---|---|
Double-node upsets induced by the charge sharing effects are emerging as a major reliability issue in nanometer latch design. Although the existing robust latches can provide a good tolerance for double-node upsets, the implementation of these hardened latches incurs in considerable hardware penalties in terms of delay, area, and power, because they rely on traditional hardening techniques such as... |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCSI.2020.2973676 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Latches,Radiation hardening (electronics),Transistors,Redundancy,Hardware,Digital storage | Journal | 67 |
Issue | ISSN | Citations |
6 | 1549-8328 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jing Guo | 1 | 45 | 6.52 |
| Shanshan Liu | 2 | 5 | 4.50 |
| Lei Zhu | 3 | 9 | 2.29 |
| Fabrizio Lombardi | 4 | 1985 | 259.25 |