Paper Info
Title
63.2pS at 1.2V dynamic comparator in 65nm CMOS technology
Abstract
A high speed dynamic comparator is proposed. The speed of the comparator is improved by reducing the voltage of the shared nodes of the input stage and latch stage. The proposed dynamic comparator has been designed and simulated using 65nm CMOS technology. The simulation results show that the proposed comparator achieved 63.2ps delay at 1.2V power supply.
Year
DOI
Venue
2019
10.1109/ISOCC47750.2019.9027693
2019 International SoC Design Conference (ISOCC)
Keywords
DocType
ISSN
high speed,dynamic comparator,shared nodes
Conference
2163-9612
ISBN
Citations 
PageRank 
978-1-7281-2479-7
0
0.34
References 
Authors
0
2
Name
Order
Citations
PageRank
Jun Yuan124423.10
Xiaobin Tang200.34