Name
Abstract | ||
|---|---|---|
3-D triple-level cell (3-D TLC) NAND flash has high storage density and capacity, but degrading data reliability due to high raw bit error rates induced by a certain number of program/erase cycles. To guarantee data reliability, low-density parity-check (LDPC) codes are selected as the error correction codes in modern flash memories because of strong error correction capability. However, directly ... |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCAD.2019.2897706 | IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems |
Keywords | DocType | Volume |
Decoding,Iterative decoding,Reliability,Bit error rate,Sparse matrices | Journal | 39 |
Issue | ISSN | Citations |
4 | 0278-0070 | 3 |
PageRank | References | Authors |
0.40 | 0 | 8 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Fei Wu | 1 | 104 | 35.76 |
| Meng Zhang | 2 | 16 | 5.23 |
| Yajuan Du | 3 | 8 | 5.21 |
| Weihua Liu | 4 | 5 | 1.51 |
| Zuo Lu | 5 | 4 | 0.77 |
| Jiguang Wan | 6 | 29 | 9.71 |
| Zhi-hu Tan | 7 | 4 | 1.11 |
| Changsheng Xie | 8 | 32 | 9.93 |