Name
Abstract | ||
|---|---|---|
To speed up the FPGA placement and routing closure, we propose a novel approach to predict the routing congestion map for large-scale FPGA designs at the placement stage. After reformulating the problem into an image translation task, our proposed approach leverages recent advancement in generative adversarial learning to address the task. Particularly, state-of-the-art generative adversarial networks for high-resolution image translation are used along with well-engineered features extracted from the placement stage. Unlike available approaches, our novel framework demonstrates a capability of handling large-scale FPGA designs. With its superior accuracy, our proposed approach can be incorporated into the placement engine to provide congestion prediction resulting in up to 7% reduction in routed wirelength for the most congested design in ISPD 2016 benchmark. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ASP-DAC47756.2020.9045178 | 2020 25th Asia and South Pacific Design Automation Conference (ASP-DAC) |
Keywords | DocType | ISSN |
well-engineered features extraction,ISPD 2016 benchmark,generative adversarial learning,FPGA placement,high-resolution image translation,state-of-the-art generative adversarial networks,routing congestion map,routing closure,high-definition routing congestion prediction,routed wirelength,placement engine,large-scale FPGA designs | Conference | 2153-6961 |
ISBN | Citations | PageRank |
978-1-7281-4124-4 | 1 | 0.35 |
References | Authors | |
10 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Mohamed Baker Alawieh | 1 | 34 | 7.63 |
| Wuxi Li | 2 | 36 | 6.03 |
| Yibo Lin | 3 | 119 | 20.98 |
| Love Singhal | 4 | 61 | 6.22 |
| Mahesh A. Iyer | 5 | 5 | 2.13 |
| David Z. Pan | 6 | 2653 | 237.64 |