Paper Info
Title
Vertical Sidewall MoS<inf>2</inf> Growth and Transistors
Abstract
We present novel growth of the two-dimensional (2D) semiconductor MoS <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> directly on oxide/Si sidewalls as deep as <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$3\ \mu \mathrm{m}$</tex> , demonstrating the first vertical 2D transistors with <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{o}\mathrm{n}}/I_{\mathrm{off}} &gt; 10^{7}$</tex> and <tex xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">$I_{\mathrm{o}\mathrm{n}}\approx 30\mu \mathrm{A}/\mu \mathrm{m}$</tex> , showing promise for high-density memory selector applications. We also demonstrate direct growth on high-k AbO <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> , an important step towards realizing VLSI-compatible 2D transistors. Our results show that 2D semiconductors can be implemented on non-planar surfaces with amorphous dielectrics for 3D back-end-of-line (BEOL) integration and high-density vertical memory selectors.
Year
DOI
Venue
2019
10.1109/DRC46940.2019.9046476
2019 Device Research Conference (DRC)
Keywords
DocType
ISSN
3D back-end-of-line integration,high-density memory selector applications,two-dimensional semiconductor growth,vertical sidewall growth,vertical sidewall transistors,vertical 2D transistors,high-k materials,VLSI-compatible 2D transistors,nonplanar surfaces,amorphous dielectrics,MoS2-Si,Al2O3
Conference
1548-3770
ISBN
Citations 
PageRank 
978-1-7281-2113-0
0
0.34
References 
Authors
0
5
Name
Order
Citations
PageRank
Connor J. McClellan101.01
Andrew C. Yu200.34
Ching-Hua Wang300.34
H.-S. Philip Wong4645106.40
Eric Pop55012.07