Abstract | ||
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Network measurement is critical for many network functions such as detecting network anomalies, accounting, detecting elephant flow and congestion control. Recently, sketch based solutions are widely used for network measurement because of two benefits: high computation efficiency and acceptable error rate. However, there is usually a tradeoff between accuracy and memory cost. To make a reasonable tradeoff, we propose a novel sketch, namely the HBL (Heavy-Buffer-Light) sketch in this paper. The architecture of HBL sketch is three-tier consisting of heavy part, buffer layer and light part, which can be viewed as an improved version of Elastic sketch which is the state-of-the-art in network measurement. Compared to the Elastic sketch and other typical work, HBL sketch can reduce the average relative error rate by 55%-93% with the same memory capacity limitations. |
Year | DOI | Venue |
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2019 | 10.1007/978-3-030-38991-8_4 | ALGORITHMS AND ARCHITECTURES FOR PARALLEL PROCESSING (ICA3PP 2019), PT I |
Keywords | DocType | Volume |
Network measurement, Sketch, Tradeoff, Average, Relative Error | Conference | 11944 |
ISSN | Citations | PageRank |
0302-9743 | 0 | 0.34 |
References | Authors | |
0 | 6 |
Name | Order | Citations | PageRank |
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Keyan Zhao | 1 | 0 | 0.34 |
Jun-xiao Wang | 2 | 2 | 1.71 |
heng qi | 3 | 44 | 10.17 |
Xin Xie | 4 | 103 | 15.93 |
Xiaobo Zhou | 5 | 64 | 16.25 |
Keqiu Li | 6 | 1415 | 162.02 |