Name
Abstract | ||
|---|---|---|
The Neoverse family of Arm processors target a combination of high performance and compute density, enabling scalable computing platforms to power the internet infrastructure, from IoT gateways to datacentre servers. The first-generation CPU in the series (the N1) is an Arm Architecture v8.2 compliant CPU and a microarchitecture optimized for infrastructure applications [5]. Compared to the previous-generation core (Cortex-A72) [1], the N1 CPU provides 60% higher performance at the same frequency, and a 30% power efficiency gain in the same process technology (Fig. 8.3.1). |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ISSCC19947.2020.9062889 | 2020 IEEE International Solid- State Circuits Conference - (ISSCC) |
Keywords | DocType | ISSN |
previous-generation core,power efficiency gain,FinFET,infrastructure applications,Neoverse family,Arm processors,compute density,scalable computing platforms,Internet infrastructure,IoT gateways,first-generation CPU,Arm Architecture v8.2 compliant CPU,ARM Neoverse N1 CPU,data centre servers,Cortex-A72,process technology,frequency 3.0 GHz,size 7.0 nm,efficiency 30 percent | Conference | 0193-6530 |
ISBN | Citations | PageRank |
978-1-7281-3206-8 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Robert Christy | 1 | 0 | 0.34 |
| Stuart Riches | 2 | 0 | 0.34 |
| Sujil Kottekkat | 3 | 0 | 0.34 |
| Prasanth Gopinath | 4 | 0 | 0.34 |
| Ketan Sawant | 5 | 0 | 0.34 |
| Anitha Kona | 6 | 3 | 0.69 |
| Rob Harrison | 7 | 118 | 8.62 |