Name
Title | ||
|---|---|---|
The Price for Asynchronous Execution of Extern Functions in Programmable Software Data Planes |
Abstract | ||
|---|---|---|
Target-independent packet processing languages such as P4 support diverse hardware and software targets by generalizing over the set of primitive operations available on the target. Architecture models declare extern functions through which functionalities of the underlying target can be accessed. Though they can be invoked at any location in the packet processing pipeline, their implementation details are opaque to the data plane program. In P4, the language specification does not define whether the extern function calls are synchronous or asynchronous control statements - supposedly synchronous by default. However, there are use cases when the asynchronous invocation makes more sense, letting the main thread keep processing packets while the extern operation is being performed by a dedicated resource (dedicated thread, CPU core or GPU) or an accelerator device (cryptographic co-processor or accelerator card). This paper examines how asynchronous extern function calls can be implemented in high-performance software data planes defined in P4, what overheads must be taken into account and which factors affect the price we have to pay for the asynchronous invocation. Our evaluation reveals the trade-off between the packet processing performance and the ratio of the computational cost of the extern function to the overhead caused by the asynchronous execution model. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ICIN48450.2020.9059357 | 2020 23rd Conference on Innovation in Clouds, Internet and Networks and Workshops (ICIN) |
Keywords | DocType | ISSN |
programmable software data planes,target-independent packet processing languages,software targets,packet processing pipeline,data plane program,language specification,asynchronous control statements,asynchronous invocation,high-performance software data planes,packet processing performance,asynchronous execution model,architecture models,accelerator device,cryptographic co-processor,accelerator card,asynchronous extern function calls,P4 support diverse hardware,synchronous control statements,computational cost ratio | Conference | 2162-3414 |
ISBN | Citations | PageRank |
978-1-7281-5128-1 | 0 | 0.34 |
References | Authors | |
0 | 7 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sándor Laki | 1 | 86 | 13.09 |
| Dániel Horpácsi | 2 | 36 | 5.48 |
| Péter Vörös | 3 | 2 | 2.41 |
| Máté Tejfel | 4 | 0 | 0.34 |
| Péter Hudoba | 5 | 0 | 0.34 |
| Gergely Pongrácz | 6 | 68 | 16.25 |
| László Molnár | 7 | 0 | 0.68 |