Title
A Ka-Band CMOS Phase-Inverting Amplifier with 0.6 dB Gain Error and 2.5° Phase Error
Abstract
This paper demonstrates the design of a Ka-band 0°/180° phase-inverting amplifier (PIA) based on a 3-port transformer in 65-nm CMOS technology. Cascode topology with common-gate (CG) switch is employed to increase the reverse isolation and gain. Layout optimization techniques including double parallel inductors and self-resonant capacitor are used to improve the balance performance. The proposed PIA achieves 10.4 dB gain at 26.5 GHz with 3-dB bandwidth of over 6 GHz (i.e., 24-30 GHz). The maximum measured gain and phase errors are 0.6 dB and 2.5°, respectively. The DC power consumption is only 2.4 mW with 1-V supply.
Year
DOI
Venue
2019
10.1109/A-SSCC47793.2019.9056917
2019 IEEE Asian Solid-State Circuits Conference (A-SSCC)
Keywords
DocType
ISBN
phase-inverting amplifier (PIA),millimeter-wave,double parallel inductors,self-resonant capacitor,CMOS
Conference
978-1-7281-5107-6
Citations 
PageRank 
References 
0
0.34
2
Authors
2
Name
Order
Citations
PageRank
Chenyu Xu100.34
Dixian Zhao211918.35