Paper Info
Title
Flexible Hardware Approach To Multi-Core Time-Predictable Systems Design Based On The Interleaved Pipeline Processing
Abstract
The study presents a hardware-based approach to modelling and design of time-predictable electronic embedded systems. It addresses multithread and multitask problems of contemporary real-time systems. Authors propose a universal template of the reconfigurable system architectures that can be flexibly accommodated to a given application. The synthesisable and parametrised model of the system architecture has been implemented in VERILOG. The architecture is based on ARM-like RISC solutions and its heart, the main core, is built of 8-12 stage reconfigurable pipelining with the interleaving mechanism. This core is a basic building block of the system and it can be replicated. Each core can handle several hardware threads with replicated register files. The entire structure has a deadline controlling mechanism that is responsible for tasks' evaluation predictability. The authors analyse the coherency of the proposed memory system and interoperability between hardware threads. Three different static scheduling algorithms have been developed and presented in examples. This study contains the results of the simulation experiments and the summary of the hardware implementation in Virtex-7 FPGA platforms. Authors have investigated the timing parameters of the system and pointed out the areas for further research.
Year
DOI
Venue
2020
10.1049/iet-cds.2019.0521
IET CIRCUITS DEVICES & SYSTEMS
Keywords
DocType
Volume
reduced instruction set computing, multi-threading, pipeline processing, field programmable gate arrays, processor scheduling, flip-flops, logic design, multiprocessing systems, interleaved pipeline processing, hardware-based approach, time-predictable electronic embedded systems, reconfigurable system architectures, ARM-like RISC solutions, hardware threads, replicated register files, deadline controlling mechanism, memory system, flexible hardware approach, multicore time-predictable systems design, reconfigurable pipelining, Virtex-7 FPGA platforms
Journal
14
Issue
ISSN
Citations 
5
1751-858X
0
PageRank 
References 
Authors
0.34
0
2
Name
Order
Citations
PageRank
Ernest Antolak100.34
Andrzej Pulka200.34