FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON - Citegraph

Paper Info

Title
FPGA Implementation of Deep Neural Network Based Equalizers for High-Speed PON

Year	DOI	Venue
2020	10.1364/ofc.2020.t4d.2	OFC
DocType	Citations	PageRank
Conference	0	0.34
References	Authors
0	8

Authors (8 rows)

Cited by (0 rows)

References (0 rows)

Name	Order	Citations	PageRank
Noriaki Kaneda	1	0	0.68
Ziyi Zhu	2	0	0.68
Chun-Yen Chuang	3	0	0.34
Amitkumar Mahadevan	4	0	1.01
Bob Farah	5	0	0.34
Keren Bergman	6	669	64.58
Doutje Van Veen	7	0	0.34
Vincent Houtsma	8	12	7.06

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