Name
Abstract | ||
|---|---|---|
In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where
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maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TCSI.2020.2977146 | IEEE Transactions on Circuits and Systems I: Regular Papers |
Keywords | DocType | Volume |
Clocks,Delays,Linearity,Computer architecture,Delay lines,Phase locked loops,Latches | Journal | 67 |
Issue | ISSN | Citations |
8 | 1549-8328 | 0 |
PageRank | References | Authors |
0.34 | 0 | 6 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Xin Cheng | 1 | 1 | 7.17 |
| Wanjing Shao | 2 | 0 | 0.34 |
| Lixin Xu | 3 | 0 | 0.34 |
| Yongqiang Zhang | 4 | 43 | 9.06 |
| Guangjun Xie | 5 | 8 | 7.32 |
| Zhang Zhang | 6 | 5 | 8.09 |