Abstract | ||
---|---|---|
Resistive nonvolatile memories (NVMs) promise significant performance improvement over existing NVM candidates. However, fabrication nonidealities and parasitics on the access path cause cell location-dependent variations in the total resistance received at the read circuitry. Write characteristics delivered to each cell, as well as the optimal write conditions for each cell, are also location-dep... |
Year | DOI | Venue |
---|---|---|
2020 | 10.1109/TVLSI.2020.2975589 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
Calibration,Delays,Resistance,Nonvolatile memory,Fabrication,Random access memory,Capacitance | Journal | 28 |
Issue | ISSN | Citations |
6 | 1063-8210 | 0 |
PageRank | References | Authors |
0.34 | 0 | 4 |
Name | Order | Citations | PageRank |
---|---|---|---|
Albert Lee | 1 | 62 | 8.49 |
Raahul Jagannathan | 2 | 0 | 0.34 |
Di Wu | 3 | 36 | 5.37 |
Kang L. Wang | 4 | 2 | 1.40 |