Name
Abstract | ||
|---|---|---|
Incorporating a soft processor in a programmable logic system, e.g. a field programmable gate array (FPGA), often requires using a substantial percentage of the logic cells (LC), notably on low-power devices. In this work we present a 32-bit RISC-V soft processor design that uses a serial arithmetic logic unit (ALU). The design can be configured to use less than 5% of the LC resources in a 5K LC low-power FPGA device. Small occupancy soft processors enable complex control and ancillary support to the principal processing and transport paths. |
Year | DOI | Venue |
|---|---|---|
2019 | 10.1109/IEEECONF44664.2019.9048878 | CONFERENCE RECORD OF THE 2019 FIFTY-THIRD ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS |
Keywords | DocType | ISSN |
Programmable logic, Low power, Soft processor, FPGA, RISC-V, Serial ALU, Sensor-hub | Conference | 1058-6393 |
Citations | PageRank | References |
0 | 0.34 | 0 |
Authors | ||
3 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Christopher Felton | 1 | 0 | 0.68 |
| Barry K. Gilbert | 2 | 0 | 0.34 |
| Clifton R. Haider | 3 | 0 | 0.34 |