Name
Abstract | ||
|---|---|---|
The von Neumann architecture is approaching its limits in terms of scalability and power consumption. In-memory computation is a possible approach to mitigate this limitation. This brief proposes a configurable 8T static random access memory (SRAM) cell with double word lines and three read ports for in-memory computing. In addition to the normal SRAM function, XOR/XNOR and compound Boolean logic operations of three or four operands, such as AND-OR, AND-OR-INVERT, OR-AND, and OR-AND-INVERT, can be performed in one cycle by fully utilizing the three read ports to obtain 13.2-fJ/bit consumption at 0.6 V. The logic operation frequency is 793 MHz at 1.2 V. The proposed SRAM effectively resolves the bottleneck of the existing in-memory computation schemes that only support compound Boolean logic operations with more than two cycles. In addition, the proposed SRAM array scheme can be configured and used as a binary content-addressable memory or a ternary content-addressable memory for searching operations; it achieves 0.24 fJ/search/bit at 0.6 V in the worst case. At 1.2 V, the searching frequency is up to 813 MHz when searching 128 bits with 65-nm technology. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TVLSI.2020.2976099 | IEEE Transactions on Very Large Scale Integration (VLSI) Systems |
Keywords | DocType | Volume |
Binary content-addressable memory (BCAM),compound Boolean logic operations,in-memory computing,static random access memory (SRAM),ternary content-addressable memory (TCAM) | Journal | 28 |
Issue | ISSN | Citations |
5 | 1063-8210 | 2 |
PageRank | References | Authors |
0.37 | 0 | 7 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Zhiting Lin | 1 | 11 | 2.67 |
| Honglan Zhan | 2 | 2 | 0.37 |
| Xuan Li | 3 | 124 | 27.25 |
| Chunyu Peng | 4 | 30 | 10.29 |
| Wenjuan Lu | 5 | 2 | 0.71 |
| Xiulong Wu | 6 | 5 | 2.78 |
| JunNing Chen | 7 | 19 | 5.75 |