Name
Abstract | ||
|---|---|---|
Scaling of transistor towards the nano-scale era is continue with every process generation as per Moore's law. The smaller feature size of Complementary Metal-Oxide Semiconductor (CMOS) technology increases the volume of on-chip transistors. Unicore processor's chip design approaches to the end of the line due to the power wall. To accommodate increasing transistor count within power wall, open a new era of computing is called “many-core” architecture. The proliferation of on-chip cores has lead to gain in performance and throughput of chip Multi-Processor (CMP). However, it shifts the paradigm from computational to communicationcentric design. To scale many core communication, Network-on-Chip (NoC) emerges as a solution for many core System-on-Chip (SoC). |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/iNIS.2017.55 | 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) |
Keywords | DocType | ISBN |
Moore's law,Complementary Metal-Oxide Semiconductor technology,on-chip transistors,many-core architecture,on-chip cores,core communication,Network-on-Chip,System-on-Chip | Conference | 978-1-5386-1357-3 |
Citations | PageRank | References |
0 | 0.34 | 11 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Ashish Sharma | 1 | 25 | 4.89 |
| Yogendra Gupta | 2 | 0 | 0.34 |
| Sonal Yadav | 3 | 3 | 2.80 |
| Lava Bhargava | 4 | 6 | 4.56 |
| Manoj S. Gaur | 5 | 501 | 63.38 |
| Vijay Laxmi | 6 | 478 | 57.09 |