Name
Abstract | ||
|---|---|---|
The Look-Up Table (LUT) approach is an effective tool for modeling semiconductor devices in the early stages of technology development for the purpose of circuit simulation. In this paper, it is shown that the conventional LUT approach leads to significant errors for SOI circuits. The cause for this discrepancy is explained. An improved LUT approach is proposed in which an auxiliary circuit is added to the conventional LUT model in order to accurately handle SOI devices. The new approach is validated for different circuits like CMOS inverter and SRAM cells. The proposed model shows substantial improvement in accuracy with 3% error as compared to 27% error in conventional LUT model. |
Year | DOI | Venue |
|---|---|---|
2017 | 10.1109/iNIS.2017.41 | 2017 IEEE International Symposium on Nanoelectronic and Information Systems (iNIS) |
Keywords | DocType | ISBN |
Look-up Table,Small-Signal Model,Large-Signal Model,Auxiliary Circuit,FDSOI,PDSOI,Enhanced LUT | Conference | 978-1-5386-1357-3 |
Citations | PageRank | References |
0 | 0.34 | 3 |
Authors | ||
6 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Sitansusekhar Roymohapatra | 1 | 0 | 0.34 |
| Ganesh R. Gore | 2 | 0 | 0.68 |
| Akanksha Yadav | 3 | 0 | 0.34 |
| Mahesh B. Patil | 4 | 27 | 7.65 |
| Krishnan S. Rengrajan | 5 | 0 | 0.34 |
| Maryam Shojaei Baghini | 6 | 86 | 29.67 |