Title
An Architectural Study for Inference Coprocessor Core at the Edge in IoT Sensing
Abstract
In this paper, random forest (RF), convolutional neural network (CNN), and support vector machine (SVM) algorithms are evaluated in terms of accuracy and performance for one-dimensional time series data in the target application fields of wearable healthcare and factory automation, considering field programmable gate array (FPGA) and system-on-a-chip (SoC) implementations. The results show that the RF is an optimal learning/inference algorithm from the viewpoint of energy efficiency and that the CNN is effective for high-precision applications. For e,ample, in arrhythmia detection, the inference accuracies of RF and CNN are 94% and 97%, respectively. In contrast, RF is approximately 4 orders higher in energy efficiency. Ne,t, an architecture for the inference coprocessor core embedded at the edge sensor was proposed, which can efficiently implement the above RF and CNN inference algorithms. An inference-oriented data-path that accelerates CNN computation was proposed, allowing for a faster order of computation with approximately 1/8 power consumption. Additionally, a port-reconfigurable RAM that increases the memory bandwidth for RF and CNN processing was introduced, which doubles the energy efficiency for RF processing. As a result, in arrhythmia detection, heartbeat interval e,traction, and human activity classification (three wearable applications), the power consumption of the RF inference coprocessor was estimated to be 0.6 μW, 0.4 μW, and 0.4 μW, respectively, assuming a standard low-power 65-nm CMOS technology.
Year
DOI
Venue
2020
10.1109/AICAS48895.2020.9073992
2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS)
Keywords
DocType
ISBN
Coprocessor,ioT,low power inference,machine learning,soC
Conference
978-1-7281-4923-3
Citations 
PageRank 
References 
1
0.35
0
Authors
9