Name
Title | ||
|---|---|---|
A Pipeline-Based Scheduler for Optimizing Latency of Convolution Neural Network Inference over Heterogeneous Multicore Systems |
Abstract | ||
|---|---|---|
Parallelization is a common design practice for throughput improvement on multicore systems. However, the existing operating systems' schedulers for CNN inference essentially divide the computational tasks of each convolution layer onto different CPU cores and cause significant inter-core feature-map data movement. Therefore, the overall performance is often degraded. In this paper, we propose a pipeline-based scheduler for convolution neural network inference parallelization with minimal feature-map data movement requirements. The experimental results show that our approach can achieve 73% performance improvement on throughput compared to the existing multi-thread scheduler. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/AICAS48895.2020.9073977 | 2020 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems (AICAS) |
Keywords | DocType | ISBN |
embedded system,heterogeneous scheduler,parallel computing | Conference | 978-1-7281-4923-3 |
Citations | PageRank | References |
1 | 0.50 | 0 |
Authors | ||
4 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Hsin-I. Wu | 1 | 2 | 3.92 |
| Da-Yi Guo | 2 | 1 | 0.50 |
| Hsu-Hsun Chin | 3 | 1 | 0.84 |
| Tsay, Ren-Song | 4 | 368 | 72.19 |