Name
Abstract | ||
|---|---|---|
Electronic data security is of vital concern for secure communication applications of cyber-physical system (CPS) that relies on Internet-of-things (IoT) based technologies. To achieve multi-level data security, a combination of long-term secure cipher, advanced encryption standard (AES), and short-term secure cipher, PRESENT are deployed together for forming a common cipher chip. The core is used for secure audio application in an open source system-on-chip (FPGA-SoC) environment. An integrated implementation of the cores is done on FPGA-SoC and ASIC. FPGA implementation of the architecture on Xilinx xc5vlx110t-1-ff1136 FPGA device consumes 14% slices. Further, the design is implemented in SCL 180 nm CMOS ASIC technology, it takes 2×2 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
die size containing 0.867 mm
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
standard cell area. At 100 MHz clock frequency, total power consumption of the chip is 11.9 mW. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/LASCAS45839.2020.9069025 | 2020 IEEE 11th Latin American Symposium on Circuits & Systems (LASCAS) |
Keywords | DocType | ISSN |
Cryptography,AES,PRESENT,VLSI architecture,ASIC,FPGA-SoC | Conference | 2330-9954 |
ISBN | Citations | PageRank |
978-1-7281-3428-4 | 1 | 0.36 |
References | Authors | |
0 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Jai Gopal Pandey | 1 | 1 | 0.70 |
| Sanskriti Gupta | 2 | 1 | 0.36 |
| Abhijit Karmakar | 3 | 25 | 8.35 |