A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol - Citegraph

Paper Info

Title
A 32Gb/s NRZ 37dB SerDes in 10nm CMOS to Support PCI Express Gen 5 Protocol

Abstract
This paper presents the first SerDes design to demonstrate a PCI-Express 5 link with area of 0.33mm2 per lane, die edge usage per lane of 285 um, dynamic junction temperature range from -40C to 125C, energy efficiency of 11.4pJ/bit including PLL and clocking, power management including power gating for all analog blocks, continuous data rate support between 1–32 Gb/s, and supporting channel topologies with insertion loss up to 37dB at 16GHz with BER < 1e-12 in 10nm process technology.

Year	DOI	Venue
2020	10.1109/CICC48029.2020.9075947	2020 IEEE Custom Integrated Circuits Conference (CICC)
Keywords	DocType	ISSN
PCIe,SerDes,NRZ,10nm	Conference	0886-5930
ISBN	Citations	PageRank
978-1-7281-6032-0	0	0.34
References	Authors
2	18

Authors (18 rows)

Cited by (0 rows)

References (2 rows)

Name	Order	Citations	PageRank
Mike Bichan	1	0	0.34
Clifford Ting	2	0	0.34
Bahram Zand	3	0	0.34
Jing Wang	4	46	15.96
Ruslana Shulyzki	5	0	0.34
James Guthrie	6	0	0.34
Katya Tyshchenko	7	0	0.34
Junhong Zhao	8	27	7.02
Alireza Parsafar	9	0	0.34
Eric Liu	10	0	0.34
Aynaz Vatankhahghadim	11	0	0.34
Shaham Sharifian	12	0	0.34
Aleksey Tyshchenko	13	0	0.34
Michael De Vita	14	0	0.34
Syed Rubab	15	0	0.34
Sitaraman Iyer	16	2	1.21
Fulvio Spagna	17	6	2.16
Noam Dolev	18	0	0.34

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