Name
Title | ||
|---|---|---|
SysScale: Exploiting Multi-domain Dynamic Voltage and Frequency Scaling for Energy Efficient Mobile Processors |
Abstract | ||
|---|---|---|
There are three domains in a modern thermally-constrained mobile system-on-chip (SoC): compute, IO, and memory. We observe that a modern SoC typically allocates a fixed power budget, corresponding to worst-case performance demands, to the IO and memory domains even if they are underutilized. The resulting unfair allocation of the power budget across domains can cause two major issues: 1) the IO and memory domains can operate at a higher frequency and voltage than necessary, increasing power consumption and 2) the unused power budget of the IO and memory domains cannot be used to increase the throughput of the compute domain, hampering performance. To avoid these issues, it is crucial to dynamically orchestrate the distribution of the SoC power budget across the three domains based on their actual performance demands.We propose SysScale, a new multi-domain power management technique to improve the energy efficiency of mobile SoCs. SysScale is based on three key ideas. First, SysScale introduces an accurate algorithm to predict the performance (e.g., bandwidth and latency) demands of the three SoC domains. Second, SysScale uses a new DVFS (dynamic voltage and frequency scaling) mechanism to distribute the SoC power to each domain according to the predicted performance demands. This mechanism is designed to minimize the significant latency overheads associated with applying DVFS across multiple domains. Third, in addition to using a global DVFS mechanism, SysScale uses domain-specialized techniques to optimize the energy efficiency of each domain at different operating points.We implement SysScale on an Intel Skylake microprocessor for mobile devices and evaluate it using a wide variety of SPEC CPU2006, graphics (3DMark), and battery life workloads (e.g., video playback). On a 2-core Skylake, SysScale improves the performance of SPEC CPU2006 and 3DMark workloads by up to 16% and 8.9% (9.2% and 7.9% on average), respectively. For battery life workloads, which typically have fixed performance demands, SysScale reduces the average power consumption by up to 10.7% (8.5% on average), while meeting performance demands. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/ISCA45697.2020.00029 | 2020 ACM/IEEE 47th Annual International Symposium on Computer Architecture (ISCA) |
DocType | ISSN | ISBN |
Conference | 0884-7495 | 978-1-7281-4661-4 |
Citations | PageRank | References |
3 | 0.35 | 59 |
Authors | ||
7 | ||
Name | Order | Citations | PageRank |
|---|---|---|---|
| Haj-Yahya Jawad | 1 | 3 | 0.35 |
| Mohammed H. Alser | 2 | 52 | 5.34 |
| Jeremie Kim | 3 | 263 | 13.68 |
| Abdullah Giray Yaglikci | 4 | 43 | 2.51 |
| Nandita Vijaykumar | 5 | 146 | 7.55 |
| Efraim Rotem | 6 | 258 | 11.37 |
| Onur Mutlu | 7 | 9446 | 357.40 |