Name
Abstract | ||
|---|---|---|
Matrix Factorization (MF) based on Stochastic Gradient Descent (SGD) is a powerful machine learning technique to derive hidden features of objects from observations. In this article, we design a highly parallel architecture based on Field-Programmable Gate Array (FPGA) to accelerate the training process of the SGD-based MF algorithm. We identify the challenges for the acceleration and propose nove... |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/TPDS.2020.2974744 | IEEE Transactions on Parallel and Distributed Systems |
Keywords | DocType | Volume |
Field programmable gate arrays,Acceleration,Training,System-on-chip,Optimization,Partitioning algorithms,Bipartite graph | Journal | 31 |
Issue | ISSN | Citations |
8 | 1045-9219 | 2 |
PageRank | References | Authors |
0.37 | 0 | 3 |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Shijie Zhou | 1 | 195 | 35.04 |
| rajgopal kannan | 2 | 743 | 67.15 |
| Viktor K. Prasanna | 3 | 7211 | 762.74 |