Name
Title | ||
|---|---|---|
Quadruple voltage mixed quenching and active resetting circuit in 150 nm CMOS for an external SPAD |
Abstract | ||
|---|---|---|
An integrated quadruple voltage mixed quenching, and active resetting circuit (Q
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
RC) in a 150 nm CMOS process is presented in this paper. The Q
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
RC features an excess-bias voltage of 7.2 V, which is four times the 1.8 V supply voltage. The dead time can be adjusted from 7 ns to 29 ns, which corresponds to the count rate range from 34 Mcps to 142 Mcps. Post-layout simulation results for an external SPAD with an equivalent parasitic capacitance of 4 pF are reported. The achieved quenching time of the Q
<sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup>
RC is 1.75 ns, which results in 4.05 GV/s quenching slew rate, while the delay time is 1.1 ns, and the resetting time is 2.55 ns. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/DDECS50862.2020.9095565 | 2020 23rd International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS) |
Keywords | DocType | ISSN |
mixed quenching circuit,active resetting circuit,SPAD,photon counting,CMOS,dead-time controllability | Conference | 2334-3133 |
ISBN | Citations | PageRank |
978-1-7281-9939-9 | 0 | 0.34 |
References | Authors | |
2 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Alija Dervic | 1 | 0 | 0.34 |
| Bernhard Goll | 2 | 15 | 6.08 |
| Horst Zimmermann | 3 | 29 | 15.60 |