Abstract | ||
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Driveable area detection is a key component for various applications in the field of autonomous driving (AD), such as ground-plane detection, obstacle detection and maneuver planning. Additionally, bulky and over-parameterized networks can be easily forgone and replaced with smaller networks for faster inference on embedded systems. The driveable area detection, posed as a two class segmentation task, can be efficiently modeled with slim binary networks. This paper proposes a novel binarized driveable area detection network (binary DAD-Net), which uses only binary weights and activations in the encoder, the bottleneck, and the decoder part. The latent space of the bottleneck is efficiently increased (x32 -> x16 downsampling) through binary dilated convolutions, learning more complex features. Along with automatically generated training data, the binary DAD-Net outperforms state-of-the-art semantic segmentation networks on public datasets. In comparison to a full-precision model, our approach has a x14.3 reduced compute complexity on an FPGA and it requires only 0.9MB memory resources. Therefore, commodity SIMD-based AD-hardware is capable of accelerating the binary DAD-Net. |
Year | DOI | Venue |
---|---|---|
2020 | 10.1109/ICRA40945.2020.9197119 | ICRA |
DocType | Volume | Issue |
Conference | 2020 | 1 |
Citations | PageRank | References |
1 | 0.43 | 2 |
Authors | ||
7 |
Name | Order | Citations | PageRank |
---|---|---|---|
Alexander Frickenstein | 1 | 4 | 3.53 |
Manoj Rohit Vemparala | 2 | 5 | 3.25 |
Mayr Jakob | 3 | 1 | 0.43 |
Naveen Shankar Nagaraja | 4 | 94 | 3.70 |
Christian Unger | 5 | 7 | 2.59 |
Federico Tombari | 6 | 1802 | 98.90 |
Walter Stechele | 7 | 365 | 52.77 |