Name
Abstract | ||
|---|---|---|
It is commonly perceived that an HLS specification targeted for FPGAs cannot provide throughput performance in par with equivalent RTL descriptions. In this work we developed a complex design of a non-binary LDPC decoder, that although hard to generalise, shows that HLS provides sufficient architectural refinement options. They allow attaining performance above CPU- and GPU-based ones and excel at providing a faster design cycle when compared to RTL development. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/FCCM48280.2020.00058 | 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) |
Keywords | DocType | ISSN |
nonbinary LDPC decoder,RTL development,high-level specifications,HLS specification,throughput performance,equivalent RTL descriptions,architectural refinement options | Conference | 2576-2613 |
ISBN | Citations | PageRank |
978-1-7281-5804-4 | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Oscar Ferraz | 1 | 0 | 0.34 |
| Srinivasan Subramaniyan | 2 | 0 | 1.35 |
| Guohui Wang | 3 | 1088 | 60.78 |
| Joseph R. Cavallaro | 4 | 1175 | 115.35 |
| Gabriel Falcão | 5 | 64 | 16.36 |
| Madhura Purnaprajna | 6 | 0 | 1.69 |