Name
Abstract | ||
|---|---|---|
FPGA is widely used in real-time network processing such as packet classification in SDN switches due to high performance and programmability. BV-based approaches on FPGA provide a performance guarantee for multi-field packet classification, but no update latency guarantee. We thus present SplitBV for the efficient update by splitting the ruleset into subrulesets that can be performed in parallel. Results show that our approach can reduce 73% and 36% update latency on average for synthetic 5-tuple rules and OpenFlow1.0 rules respectively. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/FCCM48280.2020.00044 | 2020 IEEE 28th Annual International Symposium on Field-Programmable Custom Computing Machines (FCCM) |
Keywords | DocType | ISSN |
FPGA,real-time network,BV-based approaches,performance guarantee,multifield packet classification,update latency optimization,SDN switch,SplitBV,synthetic 5-tuple rules,OpenFlow1.0 rules | Conference | 2576-2613 |
ISBN | Citations | PageRank |
978-1-7281-5804-4 | 0 | 0.34 |
References | Authors | |
2 | 5 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Chenglong Li | 1 | 6 | 4.18 |
| Tao Li | 2 | 38 | 7.33 |
| Junnan Li | 3 | 0 | 3.38 |
| Zilin Shi | 4 | 0 | 0.68 |
| Baosheng Wang | 5 | 169 | 18.08 |