Name
Abstract | ||
|---|---|---|
Worst-case execution bounds for real-time programs are profoundly impacted by the latency of accessing hardware shared resources, such as off-chip DRAM. While many different memory controller designs have been proposed in the literature, there is a trade-off between average-case performance and predictable worst-case bounds, as techniques targeted at improving the former can harm the latter and vice-versa. We find that taking advantage of pipelining between different commands can improve both, but incorporating pipelining effects in worst-case analysis is challenging. In this work, we introduce a novel DRAM controller that successfully balances performance and predictability by employing a dynamic pipelining scheme. We show that the schedule of DRAM commands is akin to a two-stage two-mode pipeline, and hence, design an easily-implementable admission rule that allows us to dynamically add requests to the pipeline without hurting worst-case bounds. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1109/RTAS48715.2020.00-15 | 2020 IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS) |
Keywords | DocType | ISSN |
DRAMbulism,balancing performance,real-time programs,hardware shared resources,off-chip DRAM,average-case performance,worst-case analysis,novel DRAM controller,dynamic pipelining scheme,DRAM commands,two-stage two-mode pipeline,pipelining effects,memory controller designs,worst-case execution bounds | Conference | 1545-3421 |
ISBN | Citations | PageRank |
978-1-7281-5500-5 | 0 | 0.34 |
References | Authors | |
15 | 3 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Reza Mirosanlou | 1 | 0 | 0.34 |
| Mohamed A. S. Hassan | 2 | 79 | 19.44 |
| Rodolfo Pellizzoni | 3 | 1020 | 53.85 |