Name
Abstract | ||
|---|---|---|
We present a new logic synthesis framework which produces efficient post-technology mapped results on heterogeneous networks containing a mix of different types of logic. This framework accomplishes this by breaking down the circuit into sections using a hypergraph k-way partitioner and then determines the best-fit logic representation for each partition between two Boolean networks, And-Inverter Graphs (AIG) and Majority-Inverter Graphs (MIG), which have been shown to perform better over each other on different types of logic. Experimental results show that over a set of Open Piton Design Benchmarks (OPDB) and OpenCores benchmarks, our proposed methodology outperforms state-of-the-art academic tools in AreaDelay Product (ADP), Power-Delay Product (PDP), and EnergyDelay Product (EDP) by 5%, 2%, and 15% respectively after performing Application Specific Integrated Circuits (ASIC) technology mapping as well as showing a 54% improvement in runtime over conventional MIG optimization. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.23919/DATE48585.2020.9116534 | DATE |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 6 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Max Austin | 1 | 0 | 0.34 |
| Scott Temple | 2 | 1 | 1.03 |
| Walter Lau Neto | 3 | 2 | 2.05 |
| Luca Amarú | 4 | 206 | 28.41 |
| Xifan Tang | 5 | 59 | 12.89 |
| Pierre-Emmanuel Gaillardon | 6 | 355 | 55.32 |