Paper Info
Title
Binary Linear ECCs Optimized for Bit Inversion in Memories with Asymmetric Error Probabilities
Abstract
Many memory types are asymmetric with respect to the error vulnerability of stored 0's and 1's. For instance, DRAM, STT-MRAM and NAND flash memories may suffer from asymmetric error rates. A recently proposed error-protection scheme consists in the inversion of the memory words with too many vulnerable values before they are stored in an asymmetric memory. In this paper, a method is proposed for the optimization of systematic binary linear block error-correcting codes in order to maximize their impact when combined with memory word inversion.
Year
DOI
Venue
2020
10.23919/DATE48585.2020.9116531
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Keywords
DocType
ISSN
memory word inversion,asymmetric error rates
Conference
1530-1591
ISBN
Citations 
PageRank 
978-1-7281-4468-9
0
0.34
References 
Authors
0
3
Name
Order
Citations
PageRank
Valentin Gherman1363.35
Samuel Evain2736.98
Bastien Giraud35317.41