Title
Analysis of a 28-nm CMOS Fast-Lock Bang-Bang Digital PLL With 220-fs RMS Jitter for Millimeter-Wave Communication
Abstract
This article analyses and demonstrates a 22.5–27.7-GHz fast-lock low-phase-noise bang-bang digital phase-locked loop (PLL) for millimeter-wave (mm-wave) communication. A discrete-time PLL model, together with theoretical transfer functions, gives insight on the functionality of the automatic bandwidth control, on the effect of the gear-shift algorithm for fast lock and on the different noise contributions. The proposed gear-shift algorithm scales up the PLL bandwidth for faster acquisition and orderly reduces it for jitter performance. The PLL contains a digitally controlled oscillator (DCO) based on transformer feedback with a tunable source-bridged capacitor, which allows for a low phase noise (PN) over a wide tuning range (FoM of −184 dBc/Hz and FoM <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$_{T}$ </tex-math></inline-formula> of −191 dBc/Hz) and for a fine frequency resolution. The PLL occupies 0.09-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> core area and exhibits 220 fs rms jitter while consuming 25 mW, giving FoM <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">RMS</sub> of −239 dB. Its frequency acquisition time improves from 780 to 45 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{s}$ </tex-math></inline-formula> with the gear-shift algorithm. For 60-GHz communication, with a frequency multiplication factor of 2.5, this PLL covers all six channels’ frequencies of IEEE-802.11ad, allows a transmitter (TX) error vector magnitude (EVM) down to −35.9 dB assuming a TX signal to the noise-plus-distortion ratio (SNDR) of 40 dB, and, thus, is capable of supporting 256 quadrature amplitude modulation (QAM).
Year
DOI
Venue
2020
10.1109/JSSC.2020.2993717
IEEE Journal of Solid-State Circuits
Keywords
DocType
Volume
Phase locked loops,Oscillators,Bandwidth,Quadrature amplitude modulation,Jitter,OFDM,Capacitors
Journal
55
Issue
ISSN
Citations 
7
0018-9200
3
PageRank 
References 
Authors
0.39
0
6
Name
Order
Citations
PageRank
Cheng-Hsueh Tsai141.43
Zhiwei Zong242.43
Federico Pepe330.39
Giovanni Mangraviti431.07
Jan Craninckx562.86
Piet Wambacq652996.10