Paper Info
Title
The Minimizating of Hardware for Implementation of Pseudo LRU Algorithm for Cache Memory
Abstract
the synthesis of the synchronous digital automaton with the logic of the pseudo LRU algorithm is carried out taking into the account events of hits or misses inside the associative cache memory. The synchronous digital automaton's model with the controlling logic for management substitution of data elements at the full reliability of the selected data's multitude is described. The minimizating for the switching functions that are simple completely defined and composite not completely defined are carried out. They are switched as: L = λ(B) by selecting multiple among reliable values and B <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> = f(B, λ(B)) forming the values of bits for unit LRU considering the previous state. As a result the minimum discrete realization has been obtained by suggested hardware solutions substitution policy for the algorithm of pseudo LRU of internal associative cache memory.
Year
DOI
Venue
2020
10.1109/DESSERT50317.2020.9125054
2020 IEEE 11th International Conference on Dependable Systems, Services and Technologies (DESSERT)
Keywords
DocType
ISBN
algorithm pseudo LRU,synchronous digital automaton,controlling logic,internal memory cache,LRU unit
Conference
978-1-7281-9957-3
Citations 
PageRank 
References 
0
0.34
0
Authors
2
Name
Order
Citations
PageRank
Vadym Puidenko100.34
Vyacheslav Kharchenko211325.59