Name
Title | ||
|---|---|---|
Speeding up Quantified Bit-Vector SMT Solvers by Bit-Width Reductions and Extensions. |
Abstract | ||
|---|---|---|
Recent experiments have shown that satisfiability of a quantified bit-vector formula coming from practical applications almost never changes after reducing all bit-widths in the formula to a small number of bits. This paper proposes a novel technique based on this observation. Roughly speaking, a given quantified bit-vector formula is reduced and sent to a solver, an obtained model is then extended to the original bit-widths and verified against the original formula. We also present an experimental evaluation demonstrating that this technique can significantly improve the performance of state-of-the-art smt solvers Boolector, CVC4, and Q3B on quantified bit-vector formulas from the smt-lib repository. |
Year | DOI | Venue |
|---|---|---|
2020 | 10.1007/978-3-030-51825-7_27 | SAT |
DocType | Citations | PageRank |
Conference | 0 | 0.34 |
References | Authors | |
0 | 2 | |
Name | Order | Citations | PageRank |
|---|---|---|---|
| Martin Jonás | 1 | 3 | 2.48 |
| Jan Strejcek | 2 | 99 | 13.83 |